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    • 专利摘要:
    The invention relates to a method of manufacturing a hybrid nonvolatile memory device comprising the following steps: - forming a first group of electrically conductive pads (240) spaced from each other in a first zone (100a) of a substrate (100); depositing a first electrically conductive layer on a second zone (100b) of the substrate (100); - etching the first conductive layer, so as to obtain a second group of electrically conductive pads (240) spaced from each other in the second zone (100b), the etching conditions being chosen so that the conductive pads of the second zone have a section at their base smaller than at their summit; - Protect the upper face of the conductive pads (240) of the second zone (100b); subjecting the substrate to an oxidation treatment, resulting in a layer of insulating material (250, 250 ') covering the upper face of the conductive pads (240) of the first zone (100a) and the flanks of the conductive pads; (240) of the second zone (100b); depositing (F9) an oxide layer (270) at the vertices of the conductive pads (240) of the first zone (100a), whence results memory elements (270a) of a first type supported by the conductive pads the first zone; and forming by physical vapor deposition memory elements (270b) of a second type at the vertices of the conductive pads (240) of the second zone (100b), so that each memory element of the second type is supported by one conductive pads of the second zone.
    公开号:FR3027450A1
    申请号:FR1460078
    申请日:2014-10-20
    公开日:2016-04-22
    发明作者:Luca Perniola；Bernard Dieny
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] The present invention relates to the field of non-volatile memories with resistive elements, and more particularly to a memory device incorporating OxRAM-type memory elements ("Oxide Resistive"). Random Access Memory ").
    [0002] STATE OF THE ART Several non-volatile memory technologies are being developed with various degrees of maturity. It is possible in particular to mention phase-change RAMs (PCRAMs), resistive conductive bridge RAMs (CBRAM) or OxRAM oxide-based memories, ferroelectric FeRAM memories and magnetic memories. MRAM. Apart from the FeRAM memories which operate on the principle of the orientation of an electric dipole moment in a ferroelectric material, all other memories use variable electrical resistance materials. Each bit of information is stored in a memory point comprising a variable resistance element. The information bit is encoded by the resistance value of this storage element. Typically, logic level '0' corresponds to a high resistance value and logic level '1' corresponds to a low resistance value.
    [0003] The mechanism behind the variation in resistance depends on the technology used. In the PCRAM for example, it is semiconductor chalcogenide materials that can be passed from an amorphous state to a crystalline state (or vice versa) by current pulses of appropriate amplitude and duration. In MRAMs, the storage element is a magnetic tunnel junction with a tunnel magnetoresistance effect. In CBRAMs, conductive filaments are formed or destroyed by diffusing metal ions (eg Ag) into a semiconductor matrix (eg Ge). Finally, OxRAMs have a behavior similar to that of CBRAMs in the sense that a conductive filament is formed in an oxide. This filament is formed by accumulation of oxygen vacancies (at least for the family of transition metal oxides), rather than by accumulation of metal ions. All these forms of memory involve the passage of a current through the storage element, which has an electrical resistance varying between a minimum value and a maximum value. Each of these non-volatile memory technologies has advantages and disadvantages. For example, MRAMs are fast and support a number of read / write cycles almost unlimited but have a lower integration density than resistive memories of type OxRAM and CBRAM. OxRAM and CBRAM benefit from low power consumption and high integration density, but the variability of performance between memory points is important. These two types of memory also have the advantage of being integrated over a logic circuit, for example a microprocessor (integration "BEOL"). To take full advantage of these various advantages, it is customary to combine several memory technologies. Around the microprocessor, it is possible in particular to provide the MRAM (high speed and endurance) to replace the current SRAM ("Static Random Access Memory") memory levels "cache" (L-1 to L3 levels), and the PCRAM as main memory instead of Dynamic Random Access Memory (DRAM). Further from the microprocessor, the memories OxRAM and CBRAM (high density of integration and low consumption) advantageously replace the memory "Flash" as mass storage memories. At present, these different non-volatile memories are formed by as many electronic components connected on the same printed circuit (for example a motherboard). However, the integration of two (or more) types of memory within the same component, that is to say on the same semiconductor substrate, would allow more efficient processing of the information by the microprocessor. Indeed, the information flows would be increased, because of the reconciliation between the memories. The co-integration of several types of memory would also facilitate the replacement of volatile memories (SRAM, DRAM) by the non-volatile memories and improve the distribution of memories around the microprocessor. There is therefore today a need to provide a memory device combining several emerging technologies of non-volatile memory on the same substrate in order to simultaneously benefit from the advantages associated with each of these technologies. Among the OxRAM memories, we can distinguish those having a selection device (typically a transistor), which allows when reading a memory point to limit the leakage currents to the adjacent memory points, and those lo lacking such a selection device. The latter are described as "selector-less" according to the Anglo-Saxon terminology. The article [<< Selector-less ReRAM with an excellent non-linearity and reliability by the band-gap engineered multi-layer titanium oxide and triangular shaped AC pulse »; Lee S. et al., Electron Devices Meeting (IEDM), pp.10.6.1-10.6.4, 2013] discloses an exemplary OxRAM resistive memory without a selector. OxRAMs without a selector have a more compact structure (due to the absence of the selection transistor). The problem of leakage currents is solved by connecting a diode in series with the active layer formed by a metal oxide (eg HfO 2, Ta 2 O 5). This diode performs the function of selector, because the memory then has a non-linear current-voltage characteristic with a threshold voltage. The patent application US2014 / 0158967 gives another example of resistive memory OxRAM without a selector (also called "self-selective") formed by depositing a first layer of metal (for example titanium) on a substrate, oxidizing the first layer of metal to form a first oxide layer (TiO 2), then depositing a second oxide layer (eg Ta 2 O 5) and a second metal layer (eg Ta). The first and second metal layers respectively form the lower and upper electrodes. The first oxide layer 30 forms a Schottky diode with the lower electrode and the second oxide layer in contact (ohmic) with the upper electrode constitutes the active layer, seat of the formation of conductive filaments.
    [0004] To delimit the different memory points, this stack of layers is generally etched, typically by reactive plasma etching. However, for memory point sizes of less than 30 nm, this etching can cause damage to the active material, ie resistance bistable oxide (Ta205 in the example above). In addition, reactive plasma etching can cause many structural and / or chemical defects at the edges of the memory points. SUMMARY OF THE INVENTION The invention aims at integrating in the same memory device several types of memory elements (or storage elements) of variable electrical resistance on the same substrate, including elements of OxRAM type without selector, while limiting the damage and defects of the memory elements.
    [0005] This objective is fulfilled by providing a method of manufacturing a hybrid nonvolatile memory device comprising the following steps: forming a first group of electrically conductive pads spaced from each other in a first zone of a substrate; depositing a first electrically conductive layer on a second zone of the substrate; etching the first conductive layer, so as to obtain a second group of electrically conductive pads spaced from each other in the second zone, the etching conditions being chosen so that the conductive pads of the second zone have a section at their base; smaller than at the top; protect the upper face of the conductive pads of the second zone; subjecting the substrate to an oxidation treatment, resulting in a layer of insulating material covering the upper face of the conductive pads of the first zone and the flanks of the conductive pads of the second zone; depositing an oxide layer at the vertices of the conductive pads of the first zone, which results in memory elements of a first type supported by the conductive pads of the first zone; and forming, by physical vapor deposition, memory elements of a second type at the vertices of the conductive pads of the second zone, so that each memory element of the second type is supported by one of the conductive pads of the second zone. The first zone of the substrate is dedicated to OxRAM memory elements without selectors or auto-selectors. The oxide layer deposited at the vertices of the conductive pads of the first zone forms the active layer of these memory elements. It can be continuous from one memory element to another because it is electrically insulating. It does not need to be engraved to avoid a short circuit between the memory elements. The OxRAM memory elements are differentiated by the underlying conductive pads, which form lower electrodes. The second zone of the substrate is devoted to the formation of elements of a type other than those of the first zone, for example MRAM or PCRAM. In the second zone, the conductive pads have overhanging flanks (or "reentrants"), so that when the resistive material is deposited with MRAM or PCRAM memory elements, the layer of this resistive material is discretized at the tops of the pads and between the studs. In other words, the flared studs or pillars of the second zone make it possible to naturally structure the MRAM or PCRAM memory elements, without the need to etch the resistive material posteriorly. By "resistive material" is meant the material or materials that constitute the variable resistance memory element. It can be a conductive material acting as an electrode (for example the magnetic reference layer in an MRAM) or active material, that is to say one that fulfills the storage function (for example: example the phase change layer in a PCRAM).
    [0006] Thus, an etching of the resistive material is avoided, both in the first zone for the formation of the OxRAM memory elements and in the second zone for the formation of the MRAM or PCRAM memory elements. Since the step of etching the resistive material by reactive plasma etching is dispensed with, the memory elements contain fewer structural and / or chemical defects on the edges. Therefore, in each of the regions of the substrate, the hybrid memory device according to the invention has less variability from one memory point to another in terms of performance. In addition, the MRAM or PCRAM memory elements are not likely to be corroded as is generally the case with reactive plasma etching. The conductive pads are electrically insulated from each other in the first zone because the oxide layer connecting them, usually a transition metal oxide (eg HfO 2, Ta 2 O 5), is electrically insulating. In the second zone, the conductive pads are also isolated from each other, despite the presence of conductive resistive material (for example magnetic or phase-change) at the bottom of the trenches separating the flared studs, thanks to the fact that this material does not cover not the flanks at the base of the studs. Indeed, the deposition of the resistive material of the elements MRAM or PCRAM being carried out according to a substantially directive method, by physical vapor deposition (PVD) such as sputtering or evaporation, the upper part overhanging each pad prevents by shading effect the deposition of the material at the foot of the flanks.
    [0007] In addition, the electrical insulation between the flared conductive pads of the second zone is reinforced by the presence of the layer of insulating material on their sidewalls. This insulating layer is formed simultaneously on the upper face of the pads of the first zone, by subjecting all the pads of the substrate to the oxidation treatment. At the tops of the conductive pads of the first zone, the insulating layer performs the function of current rectifier, according to the principle of a diode. A behavior similar to that of OxRAM memories with selection device can then be obtained because the current-voltage characteristic of these memory points is non-linear and has a threshold voltage. Depending on the materials forming the conductive pads of the first and second zones, the material that constitutes the insulating layer on the upper face of the pads of the first zone may be different from that which constitutes the insulating layer on the flanks of the pads of the second zone. .
    [0008] As the upper face of the pads of the second zone is protected during the oxidation treatment, the insulating layer does not form there. The electrical continuity between each conductive pad and the corresponding memory element is thus ensured.
    [0009] The conductive pads of the first zone do not necessarily have overhanging flanks, like those of the second zone. Indeed, since it is useless to "cut" the metal oxide layer, they may have vertical or inclined flanks, with a section at their base greater than their top ("outgoing" sides). In a preferred embodiment of the manufacturing method, the pads of the first zone of the substrate are formed of pillars identical to those of the second zone. They are formed at the same time as the conductive pads of the second zone, by etching the first conductive layer previously deposited on the first and second zones. The etching conditions are thus chosen so that the conductive pads of the first zone also have a smaller section at their base than at their summit.
    [0010] Advantageously, the method further comprises a step of depositing a second conductive layer, for example titanium, on the first conductive layer in the first zone, the first and second conductive layers being etched simultaneously to form the conductive pads of the first zoned.
    [0011] When the memory elements of the second type (eg MRAM or PCRAM) are simultaneously formed by physical vapor deposition at the vertices of the conductive pads of the first zone and at the vertices of the conductive pads of the second zone, the method furthermore comprises, before the step of depositing the oxide layer, the following steps: - covering the conductive pads of the first and second zones of a dielectric material; etching the dielectric material in the first zone until the memory elements of the first zone are discovered; and - eliminating the memory elements of the first zone.
    [0012] The oxide layer is advantageously deposited on the first and second zones by PECVD or ALD. In an alternative implementation, the conductive pads of the first zone are formed before the deposition of the first conductive layer on the second zone, their shape may be different from that of the pads of the second zone. The method according to the invention may also have one or more of the following characteristics, considered individually or in any technically possible combination: the upper face of the conductive pads of the second zone is protected by forming in the second zone a layer protection on the first conductive layer, before the step of etching the first conductive layer; The protective layer, for example ruthenium, occupies the entire second zone and is etched at the same time as the first conductive layer to form the conductive pads of the second zone; the protective layer consists of an etching mask for etching the first conductive layer, this mask being preferentially removed after the oxidation treatment; the first conductive layer is etched by reactive plasma etching. Another aspect of the invention relates to a hybrid nonvolatile memory device comprising: a substrate having first and second regions; a plurality of electrically conductive pads disposed on the substrate and distributed between the first and second zones, the pads of the second zone having a lower section at their base than at their summit; an electrically insulating layer covering the flanks of the conductive pads of the second zone and at least the upper face of the conductive pads of the first zone; a first oxide storage layer overlying the conductive pads of the first area, resulting in a plurality of first type memory elements in the first area; and a plurality of memory elements of a second type arranged at the vertices of the conductive pads of the second zone, so that each memory element is supported by one of the conductive pads of the second zone, the memory elements of the second zone. type comprising a second electrically conductive storage layer. BRIEF DESCRIPTION OF THE FIGURES Other features and advantages of the invention will emerge clearly from the description which is given below, by way of indication and in no way limiting, with reference to the appended figures, in which: FIG. substrate on which a hybrid memory device according to the invention can be manufactured; FIGS. 2A to 2J show steps F1 to F10 of a method of manufacturing a hybrid memory device, according to a preferred embodiment of the invention; and FIGS. 3A to 3C represent steps F1 'to F3' of a hybrid memory device manufacturing method, according to an alternative embodiment of the invention. For the sake of clarity, identical or similar elements are identified by identical reference signs throughout the figures.
    [0013] DETAILED DESCRIPTION OF AT LEAST ONE EMBODIMENT A preferred embodiment of a hybrid memory device manufacturing method is described below with reference to FIGS. 1, 2A-2J. Figure 1 shows a substrate 100 which serves as a starting point for the manufacturing process, while Figures 2A to 2J show steps F1 to F10 of the manufacturing process. This method aims to integrate on the substrate 100 a group of memory points OxRAM type without a selector and a group of nonvolatile memory points of another technology, for example MRAM or PCRAM. These two groups of memory points are preferably organized into matrices. In other words, the memory points are arranged in rows and columns on the surface of the substrate 100. Each memory point comprises a memory element, or storage element, of variable electrical resistance. The substrate 100 advantageously comprises a CMOS circuit capable of addressing each memory point of the hybrid memory device and reading the data recorded in the memory element, ie the electrical resistance value of this element. This circuit comprises for example transistors electrically connected to the memory elements by one or more levels of interconnection. In FIG. 1, only the last level of interconnection before the memory points is shown in cross-section. It is formed of a layer of dielectric material 101 (for example 512 or A1203) traversed by interconnection patterns 102, such as via conductors or conductive lines, typically metal (copper, aluminum ...). These interconnection patterns 102 make it possible to electrically connect the memory elements to the CMOS circuit.
    [0014] For non-volatile memory applications, it is generally sought to integrate the storage elements as high as possible in the stack, to optimize the manufacturing process. Preferably, the conductive pillars of the hybrid memory device are formed on top of one of the last metal levels.
    [0015] The via conductors (or conductive lines) 102 are (in current technologies) typically separated by a distance d greater than or equal to 3F, where F denotes the resolution of the memory device, that is to say the minimum dimension achievable by lithography ("half-pitch" in English). This value of 3F corresponds for example to CMOS technology at the distance separating two via consecutive emerging MOSFET transistors. Of course, like any metal level of the substrate, the interconnection level of Figure 1 may comprise other patterns (type via or line) than those for electrically connecting the memory elements (and referenced 102). For example, these other patterns can connect a lower level to a higher level than the memory elements or two MOS transistors located lower in the substrate. In the case of lines, they are not necessarily traversing.
    [0016] The steps F1 to F10 described below in relation to FIGS. 2A to 2J make it possible to produce, on this starting substrate 100, vertical nanostructures connected in series with the via conductors 102 and isolated from each other. Among these vertical nanostructures, there will be distinguished memory points OxRAM type without a selector and memory points of the MRAM or PCRAM type. Thus, a first region 100a of the substrate 100 is dedicated to the formation of OxRAM type memory cells without a selector and a second zone 100b is intended for the formation of MRAM or PCRAM type memory cells (FIG. 2A).
    [0017] Step F1 of FIG. 2A consists in depositing on the substrate 100 a first electrically conductive layer 200, for example made of tantalum. This layer 200 is intended to form conductive pads on which the memory elements will be formed. The electrical resistivity of the material of the layer 200 is such that, once etched in the form of mesa, the electrical resistance of each pad is low, typically less than the maximum resistance of the memory element. This minimizes the parasitic series resistance effect, which decreases the relative signal variation when reading the state of the memory element (weakly resistive state LRS or highly resistive HRS, "Low Resistive State" or "High Resistive State" in English). Preferably, the electrical resistivity of the layer 200 is less than 2.104 gl.cm.
    [0018] The material of the conductive layer 200 may be chosen from tantalum (Ta), tungsten (W), aluminum (Al), titanium (Ti), titanium nitride (TiN) and polycrystalline silicon (poly- Si) strongly doped (concentration of dopants for example greater than 5.1018 cm-3 for phosphorus doping). All of these materials fulfill the resistivity condition above. In this preferred embodiment, the conductive layer 200 occupies the first and second zones 100a-100b of the substrate 100. In the zone 100b, the conductive layer 200 is advantageously covered with a protective layer 210, preferably in a material whose oxide is conductive, such as ruthenium or chromium. The protective layer 210 can be obtained by photolithography and etching. The ruthenium is then deposited on the areas 100a and 100b of the substrate 100, covered with an etching mask, then restricted to the area 100b by etching it in the area 100a through the mask. In zone 100a, the first conductive layer 200 is advantageously covered with a second conductive layer 220. The layer 220 is formed of a material showing rectification properties once oxidized (because, according to Lee et al. oxide has a smaller band gap than that of the bistable oxide Hf02) and thickness advantageously between 2 nm and 30 nm, preferably between 5 nm and 10 nm. The material of the layer 220 is a material whose oxide is electrically insulating, for example titanium. Like the protective layer 210 in the area 100b, the layer 220 can be limited to the area 100a by etching. The material of the layer 220 is deposited on the zone 100a and the zone 100b, the latter being covered with the layer 210, then etched until reaching the ruthenium of the layer 210. Alternatively, the material of the layer 220 is eliminated in the zone 100b by chemical mechanical polishing ("Chemical Mechanical Planarization", CM P), with stopping of the polishing on the ruthenium layer 210. In this example, the formation of the ruthenium layer 210 takes place before the formation of the layer 220. One can of course reverse the order of these steps, using the same structuring techniques (photolithography and etching of the conductive layer 220, then CMP or etching of the ruthenium layer 210 with a stop on the layer 220). In step F2 of FIG. 2B, an etching mask 230 is formed on the layers 210 and 220. In a conventional manner, the etching mask 230 may consist of a photosensitive resin, structured by photolithography, or of a material more resistant to etching than the photoresist - in this case it is called a "hard mask". The hard mask is, for example, silicon oxide (SiO 2), silicon nitride (Si 3 N 4), silicon oxynitride (SiON) or amorphous carbon.
    [0019] The solid parts of the mask 230 constitute patterns 231 located vertically above the via conductors 102 (or conductive lines) of the substrate 100 and have the shape of the memory elements that one seeks to achieve. Advantageously, each pattern 231 is centered with respect to the underlying conductive via 102 and has dimensions greater than those of the via (so that the subsequently formed stud completely covers it). For example, the patterns 231 may have a width L approaching 2F (Fig.2B). Thus, when the via 102 are periodically spaced by a distance equal to 3F, the edge-to-edge distance of the adjacent patterns 231 is of the order of F. The shape of the patterns 231 is preferably round for reasons of homogeneity of electrical properties over the entire periphery of the pads and to facilitate the realization of the hybrid device to the most advanced technological nodes (sub-20nm). Nevertheless, other forms can be envisaged, in particular square, elliptical and rectangular.
    [0020] In F3 (FIG. 2C), the conductive layers 200, 210 and the ruthenium protection layer 220 of FIG. 2B are etched through the mask 230. The etching conditions are, in this preferred embodiment, determined so as to simultaneously obtain in the zones 100a and 100b conductive studs or pillars 240 on the overhanging flanks, for example in a notched or arcuate profile. The etching technique used during this step F3 is preferably a reactive plasma etching. Indeed, this allows (in the case of the metals of the layers 200, 210 and 220) to obtain volatile etching residues that can be easily removed by pumping out of the etching reactor. A strongly isotropic plasma etching should be avoided to prevent etching under the patterns 231 of the mask 230, which would reduce the dimensions of the upper face of the pads (and therefore memory elements). The conductive pads 240 are here mainly formed of the material of the first conductive layer 200, for example tantalum, because the layer 200 has a much greater thickness than the layers 210 and 220. The thickness of the layer 200 is preferably between 4 nm and 400 nm. The studs 240 each consist of a pattern 200 'obtained by etching the tantalum layer 200, capped with a pattern 210' (respectively 220 ') coming from the protective layer 210 (respectively of the conductive layer 220) located in zone 100b (respectively in zone 100a) In an arcuate profile, the section of studs 240 varies continuously, for example by gradually increasing from the base to the top of the pillars (the upper face of the patterns 210'- 220 '). In a notched profile, the section of each stud 240 is firstly constant in a lower part of the stud, then increases abruptly in its upper part, close to the vertex. This variation of section can be continuous or discontinuous. All the aforementioned materials can be etched with reactive plasma based on fluorine (except aluminum) or chlorine (including aluminum), or even bromine. The need to make recessed flanks requires etching chemistry that can give rise to spontaneous reactions between the material and the etching gas. Chlorine-containing gases, such as HCl, Cl 2 and BCl 3, or fluorine such as SF 6, NF 3, CF 4, will therefore preferably be chosen. It is also possible to use mixtures of chlorine-based and fluorine-based gases, or mixtures of chlorine and bromine-based gases (for example, HBr is a bromine source) to create an arcuate profile. or in "barrel", while avoiding oversampling under the patterns 231 of the mask 230, the reactive etching conditions may be chosen as follows: the power of the radiofrequency electromagnetic field which generates the plasma is advantageously between 150 W and 500 W, to limit the formation of radicals based on chlorine; the bias voltage applied to the substrate holder is preferably between 15 V and 1 kV, and advantageously less than 200 V.
    [0021] These parameters can be adjusted, especially during engraving, to control the curvature of the arc. For example, an increase in the RF power makes it possible to increase the concentration of radicals and thus to increase the curvature. An increase in the polarization power tends to reduce the chemical component of the etching and thus reduce the amplitude of the barrel. The addition of a diluent gas (Ar, Xe, He, N2 ...), to reduce the concentration of chlorine in the gas phase, or the addition of a passivating gas, tends to make the plasma less reactive and therefore to reduce the spontaneous etching reactions that create the curvature of the flanks.
    [0022] To create a notched profile, a two or three step etching process can be used. During the first step, the layers 210, 220 and the upper portion of the layer 200 (typically 50% of its thickness) are etched in an anisotropic manner to obtain vertical flanks. These vertical flanks are obtained thanks to the gradual formation of a passivation layer on the walls of the etched patterns (210 ', 220' and a part of 200 '), this passivation layer then preventing lateral etching. During the last step, isotropic etching is performed to etch the remaining portion of the layer 200, vertically towards the substrate 100 but also laterally. The upper part of the layer 200 is protected by the passivation layer formed previously during the first etching step. Advantageously, an intermediate oxidation step is carried out to reinforce the passivation layer. By way of example, doped polysilicon slot pillars can be obtained by inductively coupled plasma etching based on HBr / Cl 2 / O 2 (110 sccm / 70 sccm / 2 sccm) with an ion energy between of 70 eV and 80 eV, followed by etching by a plasma based on Cl2 and SF6 (60 sccm / 3 sccm) with an energy of ions of the same order of magnitude. In the case of a conductive layer 200 made of TiN, the first etching step can be carried out with an inductively coupled plasma based on HBr / Cl 2 (100 sccm / 50 sccm), followed by an intermediate step of plasma etching. 02-based inductive probe for oxidizing the flanks, and finally an inductively coupled plasma etching based on Cl2 (possibly preceded by an identical plasma with highly energetic ions 50 eV) to remove the titanium oxide from the etching edge) .
    [0023] A stack of layers of different materials, such as that of layers 200 and 210 in zone 100b, or layers 200 and 220 in zone 100a, greatly facilitates the formation of notch pillars. Indeed, the material of the upper layer 210 or 220 may be etched anisotropically, while the material of the lower layer 200 is etched isotropically, without changing the profile of the upper layer. The patterns 210 'and 220' respectively from the layers 210 and 220 then have straight flanks while the patterns 200 'from the layer 200 have overhanging flanks (see Fig.2C).
    [0024] For example, the titanium of a Ti / Si stack and the ruthenium of an Ru / Si stack can be etched simultaneously by an inductive plasma based on oxygen and chlorine or hydrogen chloride (HCl). A dilution gas such as Ar, H2, N2 or He may optionally be added to the gas phase of the plasma. The silicon layer can then be etched using an inductively coupled SF6 or NF3 plasma, optionally diluted with argon or helium. After obtaining pillars 240 to the desired shape, the etching mask 230 is removed, preferably wet (for example in a solution of hydrofluoric acid). FIG. 2D represents a step F4 in which the pads 240 of the zones 100a and 100b are oxidized simultaneously. This can be achieved by subjecting the substrate 100 to a heat treatment (e.g., between 20 ° C and 450 ° C) under an oxidizing atmosphere or an oxygen-based plasma. This step F4 makes it possible to form an insulating layer on all the surfaces of the pads 240 exposed to the oxidation treatment, in particular on the flanks of the conductive pads 240, which reinforces their insulation. For example, an insulating layer 250 of tantalum oxide (Ta206) covers the flanks of the conductive patterns 200 'tantalum. In addition, in the particular embodiment of FIG. 2D, the ruthenium units 210 'and the titanium units 220' are also oxidized during step F4. On the one hand, an insulating layer 250 'of titanium oxide (TiO 2) is formed on the upper face of the pads 240 located in the area 100a. This oxide layer 250 'renders non-linear the current-voltage characteristic of each OxRAM memory point. Preferably, the conditions of the oxidation treatment are chosen so that only part of the conductive patterns 220 'is oxidized to form the insulating layer 250', in this case their upper part. For example, the oxidation treatment may be an annealing carried out under an atmosphere containing oxygen (O 2), at a temperature of between 350 ° C. and 400 ° C. for a duration of between 350 s and 1500 s. Thus, the portion of patterns 220 'left intact by the oxidation treatment, i.e. their lower part, can act as a lower electrode in the OxRAM memory point. When the patterns 220 'of titanium are entirely oxidized, the lower electrode of the memory points OxRAM may be constituted by the conductive pads 240.
    [0025] On the other hand, a layer 260 of ruthenium oxide (Ru0) is formed on the upper face of the pads 240 of the zone 100b. Since the ruthenium oxide is electrically conductive, an electric current can flow without discontinuity from the base of the pads 240 (in contact with the via conductors 102 of the substrate 100) to the vertices of the pads on which the elements will be deposited. memory type MRAM or PCRAM. Conversely, in zone 100a for the OxRAM memory points, electrical continuity is not necessary. The lower electrode of an OxRAM memory point without a selector can cause the bistable oxide to pass from one state to another (it is called "breakdown" of the bistable oxide) through the insulating layer 250 '.
    [0026] Thus, the protective layer 210 protects the upper face of the conductive pads 240 of the zone 100b in the sense that this upper face remains electrically conductive after the oxidation treatment. Rather than a ruthenium layer whose oxide is conductive, it is possible to use a protective layer of a conductive material that is insensitive to the oxidation treatment, for example a noble metal (Au, Ag, Pt, etc.). In step F5 represented by FIG. 2E, memory elements 270b of the MRAM or PCRAM type are formed by physical vapor deposition (PVD) at the vertices of the pillars 240 of the zone 100b. Preferably, these same elements 270b are formed simultaneously at the vertices of the pillars 240 of the zone 100a, as illustrated in FIG. 2E. Each memory element 270b is thus supported by a pillar 240 of the zone 100a or of the zone 100b.
    [0027] Sputtering is advantageously used in the deposition step F5. This technique has a certain directivity for directing the conductive resistive material deposit of the memory elements 270b to the pillars 240, especially at their apex. However, resistive material is also deposited at the bottom of the trenches located between the pillars 240, or even on a portion of the sidewalls of the pillars depending on the incidence of the deposition and the angular dispersion of the flow of atoms from the pulverized target, thus forming Residual deposits 280. At normal incidence relative to the surface of the substrate (as shown in Figure 2E), these residual deposits 280 are located around the center of the trenches. The more the sides of the pillars 240 are overhanging, the less the deposits 280 spread near the bottom of the flanks. In oblique incidence (case not shown), the deposits 280 may be located on one and the same side of the pillars 240.
    [0028] The formation of recessed flanks therefore prevents the simultaneous deposition of resistive material on two sidewalls facing each other and belonging to different pillars, which avoids a short circuit between these two pillars (even in the absence of the insulating layer 250 on the flanks). Preferably, the sputtering is collimated in order to increase the directivity of the deposit and thus reduce the extent of the residual deposits 280 at the bottom of the trenches. Residual deposits 280 can be left as they are. Thanks to the electrical discontinuity on the sides of the pillars 240, they do not significantly disturb the operation of the hybrid device. In particular, they do not create inter-pinch short circuits.
    [0029] The formation of the elements 270b at the apices of the pillars 240 may comprise the deposition of one or more resistive materials, depending on the memory technology envisaged. For example, to make a MRAM magnetic tunnel junction, a reference layer (eg a Co, Fe and B-based alloy), a tunnel barrier layer (eg MgO) and a storage layer are successively deposited. (eg an alloy containing Co, Fe and B, with concentrations identical to or different from those of the reference layer). The reference layer and the storage layer are (ferro-) magnetic, while the tunnel barrier layer is non-magnetic. The storage layer may be located above or below the tunnel barrier, the reference layer being located on the other side of the tunnel barrier with respect to the storage layer. For a PCRAM memory, the storage layer is formed of a phase change material, for example an alloy between the germanium, antimony and tellurium elements. These materials are electrically conductive. The different layers of the elements 270b can be deposited by different techniques and at different incidences.
    [0030] Step F6 of FIG. 2F consists in filling the space between the pillars 240 with a dielectric material 290 until it completely covers their storage element 270b. Various techniques of the microelectronic industry make it possible to cover, with dielectric material (generally an oxide), high form factor structures (STI type, FinFET, "damascene" gate transistor, etc.) and / or with overhanging flanks. In particular, the gas phase deposition of liquid dielectric films may be mentioned. Liquid dielectrics are similar to a gel having the flow characteristics of a liquid. By exploiting this technique, one can easily fill structures with form factors greater than 10, even up to 30. The liquid dielectric material can be selected from Si3N4, SiO2, SiOxCyHz, SiOxHy and SiOxNyHz. These materials are chosen for their electrical resistivity (advantageously p> 0.1 Q.cm) so that the leakage currents between memory points are minimized. The advantage of this technique over other gas phase deposition techniques is the absence of voids or cavities in the layer of dielectric material 290. An alternative to gas phase processes is deposition by centrifugation. In this case, a sol-gel precursor is diluted in a solvent and deposited in liquid form on the rotating substrate. Under the effect of the centrifugal force, the liquid is distributed uniformly over the surface of the substrate. The precursors polymerize and the solvent evaporates to form a dielectric material called "Spin On Glass" (SOG). The thickness of the deposited layer is controlled by the viscosity of the material and the rotational speed of the substrate. The materials thus produced may be silicas or silicones of poly-methylsiloxane, poly-metylsilsesquioxane, polyoxycarbonyl, or poly-dimethylsiloxane type. They may also be polymers, such as planarizing resins, for example that marketed by the company "Honeywell" under the name "ACCUFLO".
    [0031] In step F7 of FIG. 2G, a portion of the dielectric material layer 290 is etched until the memory elements 270b in the area 100a are discovered. This etching is preferably carried out by means of a reactive plasma. A hard mask 300 is previously formed on the dielectric material 290 in the area 100b, to protect it from etching. Then, at F8, the memory elements 270b of the zone 100a are eliminated, preferably by reactive plasma etching. Advantageously, the plasma simultaneously etches the dielectric material 290 in the area 100a and the etching ends when the insulating layer 250 'is reached. In this case, since the plasma is not selective with respect to the dielectric material 290, the mask 300 of the previous step F7 can again be used to protect the area 100b, which is also removed after the etching.
    [0032] In step F9 (FIG. 21), an oxide layer 270, preferably a transition metal oxide selected from hafnium oxides (Hf0x) and tantalum oxides (Ta0x), is deposited at the vertices of the studs. 240 from zone 100a. Each stud 240 supports a portion of this layer 270, which forms a memory element 270a of the OxRAM type, and more particularly of the OxRAM type without a selector in the presence of the insulating layer 250 '. The oxide layer 270 may also be deposited on the dielectric material 290 located between the pads 240 of the zone 100a and thus connect the different pads 240. Nevertheless, since it is electrically insulating, the oxide layer 270 does not cause any damage. short circuit between the different memory points of the OxRAM matrix. The surface of the substrate is preferably flat in zone 100a, thanks to the fact that the plasma etching of step F8 is anisotropic. As illustrated in FIG. 21, the oxide layer 270 also covers the dielectric material layer portion 290 located in the zone 100b and in which the memory elements 270b (MRAM or PCRAM) are buried. Thus, the oxide layer 270 does not disturb the operation of the memory elements 270b. Preferably, the oxide layer 270 is deposited over the entire surface of the substrate by a conformal deposition technique, such as Plasma-Enhanced Chemical Vapor Deposition (PECVD) or atomic layers ("Atomic Layer Deposition", ALD). The fact of depositing, in the step F5 of FIG. 2E, the MRAM elements (or PCRAM) on the two zones 100a and 100b of the substrate greatly simplifies the PVD step.
    [0033] Moreover, the process up to FIG. 2F can thus be identical to that making it possible to form a unique MRAM memory device (or PCRAM). An alternative to the steps of forming the memory elements 270a and 270b (FIGS. 2E-2I) consists in protecting the zone 100a of the OxRAMs from a dielectric material before the PVD deposition of the memory elements 270b of the MRAM or PCRAM type, so that they are only formed in zone 100b. Then, these elements 270b are covered with dielectric material, while the layer of dielectric material in the area 100a is removed to release the upper face of the pads 240 located in this area. The oxide layer 270 can then be deposited in the zone 100a, and (optionally) on the dielectric material of the zone 100b. FIG. 2J shows the last step of the manufacturing process, in which electrical contacts 310 are formed at the vertices of the memory elements 270a and 270b. The contacts 310 are preferably obtained by a "damascene" type process. This "damascene" method conventionally comprises the deposition of dielectric material (here limited to the first zone 100a to obtain a plane surface on the entire substrate), the etching of cavities in the dielectric material until reaching the memory elements 270a and 270b, then filling the cavities with a conductive material, usually a metal (AI, Cu, TiN / Ti ...).
    [0034] Thanks to this manufacturing method, it is now possible to manufacture a compact and efficient hybrid memory device comprising a plurality of OxRAM memory points (without a selector) in the area 100a of the substrate 100 and a plurality of MRAM or PCRAM memory points in the adjacent area 100b. Each memory point is formed of a vertical nanostructure having as a base a conductive pad 240. The OxRAM memory points has an insulating storage layer 270a, while the MRAM or PCRAM memory cells each comprise a memory element 270b provided with a least one conductive storage layer.
    [0035] This method is particularly simple to implement, since several steps are common to the first and second zones 100a-100b of the substrate, in particular the steps of forming conductive pads 240 (in the embodiment of FIGS. 2A to 2J) and step F4 oxidation conductive pads. Indeed, this last step simultaneously forms the rectification layer in the zone 100a and insulating flanks in the zone 100b (and possibly in the zone 100b, although such flanks are useless there).
    [0036] Many variations and modifications of the hybrid memory device manufacturing method will be apparent to those skilled in the art. In particular, the order in which the two types of memory elements are formed is likely to vary. In addition, the manufacturing method, heretofore described in connection with FIGS. 2A to 2J, may not employ the second conductive layer 210 and / or the protective layer 220 made of ruthenium or noble metal. In order to protect the upper face of the pads 240 in the MRAM / PCRAM zone 100b, it is possible in particular to use the etching mask 230 (used in the step F3 for etching the pads 240; FIG. oxidation F4 and remove it only after. The etching mask 230 (or more exactly its patterns 231 located in the area 100b) then constitutes the protective layer. It is also possible to deposit at the vertices of the pads 240 of the zone 100b another so-called sacrificial protective material, such as a silicon nitride (SiN, Si3N4, SiOCN, SiNH) or a silicon oxide (SiO2). The protective material is removed after the oxidation step F4, to make conductive again the upper face of the pillars 240. In these two cases, the conductive pads 240 of the zone 100b consist solely of the material of the conductive layer 200. Similarly, if the second conductive layer 210 is dispensed with, the conductive pads 240 of the zone 100b consist solely of the patterns 200 'coming from the first conductive layer 200. It is therefore the upper portion of these patterns. 200 'which will be oxidized in step F4 and which will act as a rectification layer in the OxRAM, while the lower portion of the patterns 200' will act as an electrode. Finally, FIGS. 3A to 3C show an alternative embodiment of the manufacturing method in which the conductive pads of the OxRAM zone 100a are formed before the conductive pads of the MRAM zone or PC RAM 100b. In step F1 '(FIG. 3A), conductive pads 240a are formed in the first zone 100a of the substrate 100, for example by photolithography and etching. These pads 240a are preferably formed of the material of the second conductive layer 220 described above, that is to say a material having rectification properties once oxidized, for example titanium. The first conductive layer 200 is then deposited on the zone 100b, and preferably on the entire surface of the substrate 100, then advantageously covered by the protective layer 220.
    [0037] In F2 '(Fig.3B), the conductive layer 200 and the protective layer 220 are etched to form the conductive pillars 240b in the area 100b and fully withdrawn in the area 100a, so as to release the conductive pads 240a located at the surface of the substrate 100. The pads 240a can be of compacted shape compared to the pillars 240b and have vertical sides. This is not problematic since it is useless to discretize the active layer (270) of the OxRAM memory points. Thus, in this implementation variant, the conductive pads 240a of the zone 100a may be of different shape and type than the conductive pads 240b of the zone 100b. In addition, they constitute the lower electrode of the OxRAM memory points. The remainder of the manufacturing process, represented by step F3 'of FIG. 3C, is carried out as described above in relation to FIGS. 2D to 2J (steps F4 to F10). It should be noted that, because of their lower height, the pads 240a of the zone 100a require electrical contacts 310 which are deeper than those of the pillars 240b located in the adjacent zone 100b, and that the residual deposits 280 of MRAM or PCRAM resistive material. can be easily removed in the OxRAM zone 100a (by completely removing the dielectric material 290 in the area 100a, in step F7 of Figure 2G). Apart from the elements mentioned above, the hybrid memory device illustrated in FIG. 3C is identical to that of FIG. 2J. The elements taken back bear the same reference signs.
    权利要求:
    Claims (15)
    [0001]
    REVENDICATIONS1. A method of manufacturing a hybrid nonvolatile memory device comprising the steps of: - forming (F1-F3; F1 ') a first group of electrically conductive pads (240; 240a) spaced apart from one another in a first region (100a ) a substrate (100); depositing (F1) a first electrically conductive layer (200) on a second zone (100b) of the substrate (100); - etching (F3) the first conductive layer (200), so as to obtain a second group of electrically conductive pads (240; 240b) spaced from each other in the second zone (100b), the etching conditions being chosen so that that the conductive pads of the second zone have a section at their base smaller than their top; - Protect the upper face of the conductive pads (240, 240b) of the second zone (100b); subjecting (F4) the substrate to an oxidation treatment, resulting in a layer of insulating material (250, 250 ') covering the upper surface of the conductive pads (240; 240a) of the first zone (100a) and the flanks of the conductive pads (240; 240b) of the second zone (100b); depositing (F9) an oxide layer (270) at the vertices of the conductive pads (240; 240a) of the first zone (100a), which results in memory elements (270a) of a first type supported by the conductive pads of the first zone; and - forming (F5) by physical vapor deposition of the memory elements (270b) of a second type at the vertices of the conductive pads (240; 240b) of the second zone (100b), so that each memory element of the second type is supported by one of the conductive pads of the second zone.
    [0002]
    2. The method of claim 1, wherein the conductive pads (240) of the first zone (100a) are formed at the same time as the conductive pads (240) of the second zone (100b), by etching the first conductive layer ( 200) previously deposited on the first and second zones (100a, 100b).
    [0003]
    The method of claim 2 comprising depositing a second conductive layer (220) on the first conductive layer (200) in the first region (100a), the first and second conductive layers being etched simultaneously to form the conductive pads. (240) of the first zone.
    [0004]
    The method of claim 3, wherein the second conductive layer (220) is titanium.
    [0005]
    The method of claim 1, wherein the conductive pads (240a) of the first area (100a) are formed prior to depositing the first conductive layer (200) on the second area.
    [0006]
    The method according to any one of claims 1 to 5, wherein the memory elements (270b) of the second type are simultaneously formed by physical vapor deposition at the vertices of the conductive pads (240; 240a) of the first zone (100a). ) and at the vertices of the conductive pads (240; 240b) of the second zone (100b), the method further comprising, before the step (F9) of depositing the oxide layer, the following steps: covering (F6) a dielectric material (290), the conductive pads (240; 240a, 240b) of the first and second regions (100a, 100b); - etching the dielectric material (290) in the first zone (100a) until discovering the memory elements (270b) of the second type located in the first zone; and - eliminating the memory elements (270b) of the second type in the first zone (100a).
    [0007]
    The method of claim 6, wherein the oxide layer (270) is deposited on the first and second regions (100a, 100b) by PECVD or ALD.
    [0008]
    The method according to any one of claims 1 to 7, wherein the upper face of the conductive pads (240; 240b) of the second zone (100b) is protected by forming in the second zone a protective layer (210) on the first conductive layer (200), before the step (F3) of etching the first conductive layer (200).
    [0009]
    The method of claim 8, wherein the protective layer (210) occupies the entire second area (100b) and is etched together with the first conductive layer (200) to form the conductive pads (240; 240b). the second zone (100b).
    [0010]
    The method of claim 9, wherein the protective layer (210) is ruthenium.
    [0011]
    11. The method of claim 8, wherein the protective layer is constituted by an etching mask (230) for etching the first conductive layer (200). 15
    [0012]
    The method of claim 11, wherein the protective layer (230) is removed after the oxidation treatment (F4).
    [0013]
    13. The method of any one of claims 1 to 12, wherein the first conductive layer (200) is etched by reactive plasma etching.
    [0014]
    A hybrid nonvolatile memory device comprising: a substrate (100) having first and second regions (100a, 100b); a plurality of electrically conductive pads (240; 240a, 240b) disposed on the substrate (100) and distributed between the first and second zones (100a, 100b), the pads of the second zone (100b) having a section at their base weaker than at the top; an electrically insulating layer (250, 250 ') covering the flanks of the conductive pads (240; 240b) of the second zone (100b) and at least the upper face of the conductive pads (240; 240a) of the first zone (100a); ); a first oxide storage layer (270) overlying the conductive pads (240; 240a) of the first region (100a), whereby a plurality of memory elements (270a) of a first type in the first region are formed; zone (100a); and a plurality of memory elements (270b) of a second type arranged at the vertices of the conductive pads (240; 240b) of the second zone (100b), so that each memory element is supported by one of the conductive pads in the second zone, the memory elements (270b) of the second type comprising a second electrically conductive storage layer.
    [0015]
    The apparatus of claim 14, wherein the memory elements (270a) of the first type are OxRAM memory elements without a selector and wherein the memory elements (270b) of the second type are PCRAM or MRAM memory elements.
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    同族专利:
    公开号 | 公开日
    EP3012880A1|2016-04-27|
    US9431608B2|2016-08-30|
    EP3012880B1|2017-11-29|
    US20160111642A1|2016-04-21|
    FR3027450B1|2016-11-04|
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1460078A|FR3027450B1|2014-10-20|2014-10-20|HYBRID NON-VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SUCH A DEVICE|FR1460078A| FR3027450B1|2014-10-20|2014-10-20|HYBRID NON-VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SUCH A DEVICE|
    EP15189988.7A| EP3012880B1|2014-10-20|2015-10-15|Hybrid non-volatile memory device and method for manufacturing such a device|
    US14/887,687| US9431608B2|2014-10-20|2015-10-20|Hybrid non-volatile memory device and method for manufacturing such a device|
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